Heretofore semiconductor recording equipment such as a SD (Secure Digital) card that is a card-type recording medium having a built-in flash memory has a ultra-compact and ultra-thin form and has been widely used to record data including images in digital cameras, portables, and so forth because of its handleability.
A flash memory incorporated in semiconductor recording equipment is a memory capable of data erasing and rewriting by blocks of a predetermined size, and there is a limitation on the number of rewrites. A multi-level flash memory is designed to allow approximately 10,000 rewrites for each physical block. When the number of rewrites exceeds 10,000, the probability of writing error occurrence is increased. Note that a method that is adopted in the event of a writing error involves a step of registering a block which encounters a writing error as an error block and a step of performing writing to a block other than the error block.
Therefore, in the case of recording a moving image on the flash memory in real time, if writing errors occur with high frequency, the rate of writing to the flash memory will be lower than the rate of produced image transfer to the flash memory. This leads to the problem of inability to perform sequential recording of moving images.
As a technology conducive to retard occurrence of this problem, there is known a conventional art for causing pseudo increase in the number of rewrites in a memory (refer to Patent Document 1).
According to this conventional art, a memory is divided into a plurality of areas, and the number of rewrites for each area is stored. On the basis of the number of rewrites for each area in storage, rewrite process in the memory is so controlled that the difference in rewrite number among the individual areas can be reduced; that is, an area subjected to fewer rewrites is prioritized for use. Such a technique for exercising rewrite control in a manner to reduce the difference in rewrite number among the areas is called “leveling”. With use of this technique, even in the case of writing data to one and the same logical block several times, physical blocks that are actually subjected to recording in a flash memory change. If the leveling is accomplished perfectly, the allowable number of rewrites in semiconductor recording equipment will be increased to a level given as: (the number of physical blocks)×(the allowable number of rewrites for each physical block).
In Patent Document 2, there is proposed a semiconductor recording apparatus composed of: a rewrite number counting section for keeping count of the number of rewrites, or the number of blocks responsible for data writing to a flash memory at the request of host device; a rewrite number reading section for reading out the total number of rewrites written to the flash memory; and a rewrite number recording section that, on the basis of the number of rewrites counted by the rewrite number counting section and the total number of rewrites read out by the rewrite number reading section, derives a new total number of rewrites, or the sum of rewrites counted since the first run, and writes the thereby obtained total number of rewrites into the flash memory. In this construction, the rewrite number recording section writes the obtained total number of rewrites into the flash memory at the instant when the number of rewrites counted since the last writing of the total number of rewrites reaches a predetermined number of times or above.
In a camera recorder or the like, image data is recorded on the whole region of a memory card. After the recorded image data is uploaded to HDD or the like, the memory card is formatted for a further recording process. In such an intended purpose, the value of (the total number of rewrites/the number of physical blocks) substantially coincides with the upper limit of the number of rewrites set for a semiconductor memory. Therefore, by effecting light emission such as a warning light as the number of rewrites approaches the upper limit, it is possible for the user to be aware of the limitations on usage of the memory.    [Patent Document 1] Japanese Unexamined Patent Publication JP-A Hei 6-302194    [Patent Document 2] Japanese Unexamined Patent Publication JP-A 2005-284659